1. Field of the Invention
The present invention relates to processors, and more particularly to sampling mechanisms of processors.
2. Description of the Related Art
One method of understanding the behavior of a program executing on a processor is for a processor to randomly sample instructions as the instructions flow through the instruction pipeline. For each sample, the processor gathers information about the execution history and provides this information to a software performance monitoring tool. Unlike tools which aggregate information over many instructions (i.g., performance counters), such an instruction sampling mechanism allows the performance analyst to map processor behaviors back to a specific instruction.
A drawback of this approach is that each sample reported to software incurs an overhead (typically due to the trap raised to inform software that the sample is ready). This overhead also has an effect on the behavior of the processor being observed and may cause a disruption of the processor performance. If this disruption dramatically changes the behavior of the processor, the disruption can contaminate any conclusions based on the instruction sample.
The contamination is particularly detrimental when the sample is not of interest to the performance monitoring software. For example, if the software wishes to analyze cache behavior of a program and a sample is reported for an add instruction (which does not use the caches) then the overhead and disruption of sampling is incurred without providing the software with any useful information.